This invention relates to integrated auto-zero instrumentation amplifiers and instrumentation amplifier circuitry incorporating programmable input offset voltage correction circuits.
FIG. 1 shows a 2-phase chopped voltage reference circuit 1 which includes a current source 5 that generates a reference current IREF. A current source 5 is coupled between ground and a conductor 2 which is connected to the gates of P-channel transistors M1 and M2. The sources of transistors M1 and M2 are connected to VDD. The drain of transistor M1 is connected to the pole of a switch S1. During an “A” phase, the pole of switch S1 is connected to conductor 2. The drain of transistor M2 is connected to the pole of a switch S2. During the “A” phase, the pole of switch S2 is connected to a conductor 3 which is connected to a first terminal of a resistor R. Conductor 2 also is connected to a terminal of switch S2 to which the drain of transistor M2 is coupled by the pole of switch S2 during a “B” phase. Conductor 3 also is connected to a terminal of switch S1 to which the drain of transistor M1 is coupled by the pole of switch S1 during the “A” phase. The second terminal 3A of resistor R is connected to circuitry that receives a switched current which flows through either transistor M1 during phase “B” or transistor M2 during phase “B”.
FIG. 1A shows a waveform of the voltage VREF developed across resistor R by the currents from transistors M1 and M2 that are switched through resistor R by switches S1 and S2, respectively. Switches S1 and S2 are both controlled in response to a square wave signal at the desired chopping frequency. The illustrated “ripple” of the square wave VREF waveform with upper voltage levels of VREFH and lower voltage levels of VREFL shown in FIG. 1A is caused by normal mismatches between transistors M1 and M2. The average value of the VREF waveform is indicated by the dashed horizontal line 7.
Referring to FIG. 2, two-phase auto-zeroing instrumentation amplifier 10A includes a first input amplifier 11 having a (+) input coupled by input conductor 14A to receive input signal Vin+, a (−) input coupled to conductor 16A, and an output 15A coupled by a resistor R1 to conductor 16A. Instrumentation amplifier 10A also includes a second input amplifier 12 having a (+) input coupled by input conductor 14B to receive input signal Vin−, a (−) input coupled to conductor 16B, and an output 15B coupled by a resistor R3 to conductor 16B. A resistor R2 is connected between conductors 16A and 16B.
Instrumentation amplifier 10A also includes an output amplifier 13 having a (+) input connected by a conductor 17A to one terminal of a resistor R4 having its opposite terminal connected to output 15A of input amplifier 11 and also connected to one terminal of a resistor R6 having its opposite terminal connected to an AC ground. Output amplifier 13 also has a (−) input connected by a conductor 17B to one terminal of a resistor R5 having its opposite terminal connected to output conductor 15B of input amplifier 12. The (−) input of output amplifier 13 also is connected to one terminal of feedback resistor RF, the opposite terminal of which is connected to an output 18 of output amplifier 13. An output voltage Vout is produced on conductor 18 of output amplifier 13.
Instrumentation amplifier 10A also includes a two-phase chopped voltage reference circuit 1 that can be similar or identical to the one shown in FIG. 1, having a (+) terminal connected by conductor 3 to input amplifier 11 and a (−) terminal connected by conductor 3A to input amplifier 12.
All of the switches in FIG. 2 are illustrated as being set to the states they assume during the “A” phase of the auto-zero cycle of instrumentation amplifier 10A. It may be seen that during the auto-zeroing phase of instrumentation amplifier 10A, the two auto-zero stages labeled “A” are in their auto-zero calibration mode whereas the auto-zero stages labeled B are in a signal passing mode wherein they pass signals on to their respective output stages (i.e., output stage 39 or output stage 60). Therefore, during the “A” phase, the “A” auto-zero stage outputs are at a voltage level which is a function of VREF, mismatches between the input transistors of the auto-zero stage, and by other factors as well. Since it is desirable to minimize the transconductance gm of the input transistors of the auto-zero calibration inputs of the input amplifiers, this output voltage level may be of a substantial and significant magnitude. (Each of the conventional auto-zero stages includes a calibration input stage (in parallel with a standard input stage) including calibration input transistors and also capacitors (not shown) to hold an offset voltage. The outputs of the auto-zero stage are fed back to the “calibration inputs” to perform the function of “zeroing” the auto-zero stage. When the input switches associated with the auto-zero stages open, the capacitors therein hold the inputs of the auto-zero stages at the voltages thereon immediately prior to the instants at which the switches are opened.) Later, when the “B” phase begins, the “A” auto-zero stage outputs will be connected to the output stage 39 or 60, and the output voltage level of each auto-zero stage will change to a level that is a function of the amplified input signal Vin=Vin+−Vin−. A transient voltage “glitch” or spike produced by the illustrated switching arrangement therefore is both mismatch-dependent and signal-dependent.
In prior art instrumentation amplifier 10A of FIG. 2, the two auto-zero stages labeled “A” are auto-zeroed to the reference voltage VREF during time period A, while the two auto-zero stages labeled “B” are auto-zeroed during time period B to the reference voltage VREF produced by chopped voltage reference circuit 1. Thus, a complete auto-zero cycle occurs during the same time period as a complete two-phase reference circuit chopping cycle.
Prior Art instrumentation amplifier 10A calibrates one of the auto-zero stages in each of input amplifiers 11 and 12 during time period A and calibrates the other auto-zero stage during time period B. Therefore, the two auto-zero stages contained in each input amplifier of instrumentation amplifier 10A are always calibrated to the reference voltage VREF when they are in alternate states. This causes the input amplifier output signals on conductors 15A and 15B to vary in accordance with the chopped voltage reference levels. Furthermore, these variations and the above mentioned errors reinforce each other at the input of output amplifier 13 and produce a voltage glitch signal twice as large as either input amplifier 11 or 12 alone would produce.
Consequently, prior art instrumentation amplifiers such as the one shown in FIG. 2 (which is included in the assignee's PGA309 sensor amplifier) exhibit relatively large output voltage glitches that limit their usefulness. The voltage glitches referred to originate from various sources related to the switching nature of auto-zero circuits and chopped current circuits.
Several of the problems causing the various problematic output glitches of prior art instrumentation amplifier 10A of FIG. 2 are addressed by the subsequently described invention. The first problem of the prior art instrumentation amplifier 10A in FIG. 2 is a “clock feed-through glitch” that originates from the alternating level of reference voltage VREF produced by chopped reference voltage circuits of the kind shown in FIG. 1. Auto-zero circuits with input offset correction require a low drift voltage reference to allow accurate input offset calibration. Chopped voltage reference sources such as the one illustrated in FIG. 1 are used to provide low drift floating reference voltage signals. It is known that these chopped voltage reference circuits have accurate and stable average output values with very low long term drift and very low long term thermal drift. However, they produce slightly alternating output signal levels that vary at the chopping frequency around the average output value, due to normal device mismatches in the chopped current mirror including transistors M1 and M2. An offset correcting amplifier using such a chopped current reference circuit to produce its input offset reference therefore will calibrate its auto-zero input stages to the high and low alternating reference voltage values VREFH and VREFL. Consequently, the alternating reference values ultimately appear as signal variations when the auto-zero stages are in their amplifying mode. The signal variations are amplified and then manifest themselves as undesired voltage glitches at the amplifier output, with amplitudes proportional to the reference variations and with a frequency equal to the chopping frequency. Unlike most voltage glitches associated with auto-zero amplifiers which are fast transient voltage spikes, the above mentioned “clock feed-through glitch” produces an alternating square-wave-like error at the clock frequency, superimposed on the output signal. The nature of this glitch makes it difficult to filter, and therefore limits the usability of the instrumentation amplifier configuration shown in FIG. 2 in many applications.
A second problem of the prior art is auto-zero stage offset-dependent charge error. This charge error is introduced when the input auto-zero stages connected to the inputs of output stages 39 and 60 are alternated in input amplifiers 11 and 12, as a result of mismatches between the input offset voltages of the switched auto-zero stages being alternated.
A related third problem of the prior art is a disturbance that is propagated through output amplifier 13 to Vout each time the inputs of output stage 39 or 60 are connected to one of the auto-zero stages. This occurs because some capacitively coupled glitch energy reaches the input of output amplifier 13 each time a switch changes state and couples charge onto the signal path. Output amplifier 13 drives the output node 18 in response to these disturbances and produces an output error in Vout its until the feedback arrangement drives all affected circuit nodes back to their proper levels. A limited loop bandwidth can result in relatively long-lasting output errors in response to even very short transient voltage glitches across the input terminals of output amplifier 13.
Thus, there is an unmet need for a programmable offset-canceling instrumentation amplifier and method that produces very low-noise switching glitches and very low clock feed-through glitches.
There also is an unmet need for an offset-canceling instrumentation amplifier which substantially eliminates various voltage glitch signals characteristic of the prior art auto-zero instrumentation amplifiers.
There also is an unmet need for an offset-canceling auto-zero instrumentation amplifier which substantially eliminates the clock feed-through glitch voltages characteristic of the prior art auto-zero instrumentation amplifiers.
There also is an unmet need for an offset-canceling auto-zero instrumentation amplifier which substantially eliminates the effect of slightly alternating output signal levels of chopped current reference voltage circuits used in the prior art auto-zero instrumentation amplifiers.
There also is an unmet need for an offset-canceling auto-zero instrumentation amplifier which substantially eliminates the effects of offset-dependent charge error characteristics of the prior art auto-zero instrumentation amplifiers.
There also is an unmet need for an offset-canceling auto-zero instrumentation amplifier which substantially eliminates the effects of glitch energy that is produced and transferred to the instrumentation amplifier output each time switches associated with auto-zero stages change state in the prior art auto-zero instrumentation amplifiers.